Section 4, Semiconductor Integrated Circuits Layout-Design Act, 2000 [S20-8V1]
As at 7 September 2026. In force from 9 December 2000 by S.O. 1192(E) [N12-AG3].
4. Registration of patentees.—(1) Every patentee shall, within one month from the commencement of this Act or, where such person begins the working of a patent after such commencement, within one month from the date of such beginning, make an application for registration to the Controller in Form 3, accompanied by a fee of four thousand rupees. (2) The Controller shall, on being satisfied that the application is in order, register the applicant and issue a certificate of registration in such form as may be prescribed. (3) No patentee shall carry on the working of a patent unless registered under this section.
Defined terms in this text (4)
applicant: Section 2, Semiconductor Integrated Circuits Layout-Design Act, 2000 [S208S5] (In this Act, unless the context otherwise requires,—): "applicant" means a person who applies for registration under this Act
applicant: 3 more definitions.
Controller: Section 2, Semiconductor Integrated Circuits Layout-Design Act, 2000 [S208S5] (In this Act, unless the context otherwise requires,—): "Controller" means the Controller General of Patents, Designs and Trade Marks referred to in section 73 of the Patents Act, 1970 (39 of 1970)
Controller: 5 more definitions.
patentee: Section 2, Semiconductor Integrated Circuits Layout-Design Act, 2000 [S208S5] (In this Act, unless the context otherwise requires,—): "patentee" means the person for the time being entered on the register as the grantee or proprietor of the patent
patentee: 3 more definitions.
register: Section 2, Semiconductor Integrated Circuits Layout-Design Act, 2000 [S208S5] (In this Act, unless the context otherwise requires,—): "register" means the register maintained under section 6
register: 3 more definitions.
Made under this section, or naming it (2)
Circular of the Office of the Controller General of Patents, Designs and Trade Marks dated 28th August, 2007 on section 4 of the Semiconductor Integrated Circuits Layout-Design Act, 2000 [C10-H5D], 28 August 2007, in force. The text contains "section 4 of the Semiconductor Integrated Circuits Layout-Design Act, 2000 (37 of 2000)".
Notification S.O. 1530(E), dated 10th August, 2003 [N12-BMF], 10 August 2003, in force. The text contains "section 4 of the said Act".
Cited by (2)
Section 66, Semiconductor Integrated Circuits Layout-Design Act, 2000 [S20-ASD], 25 March 2000, Band A. "section 4".
Section 71, Semiconductor Integrated Circuits Layout-Design Act, 2000 [S20-AY3], 25 March 2000, Band A. "section 4".
Not held (0)
none
Duties published under this section (1)
D11-NBC. Every patentee: Apply for registration to the Controller in Form 3, fee four thousand rupees; thirty days from the commencement of the Act, or from beginning the activity; Form 3. Published by Office of the Controller General of Patents, Designs and Trade Marks, Ministry of Commerce and Industry (synthetic record).