Circular of the Office of the Controller General of Patents, Designs and Trade Marks dated 28th August, 2007 on section 4 of the Semiconductor Integrated Circuits Layout-Design Act, 2000 [C10-H5D]
As at 7 September 2026. In force from 28 August 2007.
F. No. 2/65/2007-OFFI
Government of India
Ministry of Commerce and Industry
Office of the Controller General of Patents, Designs and Trade Marks
New Delhi, dated the 28th August, 2007
To
All Controllers and Registrars
Subject: Section 4 of the Semiconductor Integrated Circuits Layout-Design Act, 2000 (37 of 2000), the working of a patent, regarding.
1. References have been received in the Office of the Controller General of Patents, Designs and Trade Marks seeking clarification on the manner in which section 4 of the Semiconductor Integrated Circuits Layout-Design Act, 2000 (37 of 2000) (hereinafter referred to as the Act) is to be applied to patentees who undertake the working of a patent at more than one place.
2. The matter has been examined. Section 4 of the Act requires every patentee to make an application to the Controller within the period stated in that section.
3. It is, accordingly, clarified that a separate application shall be made in respect of each place at which the working of a patent is undertaken, and the Controller shall process each application in accordance with section 4 of the Act and the rules made thereunder.
4. Difficulties, if any, in the implementation of this circular may be brought to the notice of the Office of the Controller General of Patents, Designs and Trade Marks.
(Under Secretary to the Government of India)
Made under
No enabling provision stated.
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